The present application relates generally to the manufacture of semiconductor devices, and more specifically to photolithography and masking architectures and their implementation in semiconductor device processing.
During the fabrication of semiconductor devices, features of a device on a semiconductor substrate are typically defined by a patterned mask. To provide increased feature density, the feature size is reduced, which may be achieved by reducing the critical dimension (CD) of the features. The foregoing requires improved patterning resolution, precision and accuracy.
The patterning and etching of features on the substrate typically involves forming multiple layers to affect the pattern transfer. Moreover, the various layers may be formed using distinct materials, processes, and tool sets. Simplification of the patterning architecture and associated processing without compromising pattern placement and CD control would be beneficial.